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成功大學生涯發展與就業輔導組
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* 公司名稱 :
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* 職缺項目 :
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* 工作待遇 :
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* 需求人數 :
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5
* 工作內容(含應徵方式) :
Work Description (Include Candidates Way)
1. Participate in the micro architecture and design partition within the FPGA. 2. Implement design blocks using Verilog 3. Participate in all phases of FPGA design Flow (Synthesis, Place & Route, and Timing Closure). 4. Participate in all phases of the embedded-system design flow 5. Work with SW/HW team members to bring-up and validate FPGAs and/or ASICs 6. Work with back-end company to address any layout and timing issues for ASICs. ※應徵方式: https://www.104.com.tw/job/7d5sj?jobsource=cs_2018indexpoc
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